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FEATURES Four 14-Bit DACs in One Package Voltage Outputs Separate Offset Adjust for Each Output Reference Range of 5 V Maximum Output Voltage Range of 10 V Clear Function to User-Defined Code 44-Pin MQFP Package APPLICATIONS Process Control Automatic Test Equipment General Purpose Instrumentation GENERAL DESCRIPTION
LC2MOS Quad 14-Bit DAC AD7836
The AD7836 contains four 14-bit DACs on one monolithic chip. It has output voltages with a full-scale range of 10 V from reference voltages of 5 V. The AD7836 accepts 14-bit parallel loaded data from the external bus into one of the input latches under the control of the WR, CS and DAC channel address pins, A0-A2. The DAC outputs are updated individually, on reception of new data. In addition, the SEL input can be used to apply the user programmed value in DAC Register E to all DACs, thus setting all DAC output voltages to the same level. The contents of the DAC data registers are not affected by the SEL input. Each DAC output is buffered with a gain of two amplifier into which an external DAC offset voltage can be inserted via the DUTGNDx pins. The AD7836 is available in a 44-lead MQFP package.
FUNCTIONAL BLOCK DIAGRAM
VCC VSS VDD VREF(+)A VREF(-)A VREF(+)B VREF(-)B
X1
X1
AD7836
14
DATA REG A
14 14 MUX DAC A VOUTA X1 X1 R R DUTGND A MUX DAC B VOUTB R
DB13
14
INPUT BUFFER
14 DATA REG B
DB0 WR CS
DATA REG C A0 A1 A2 ADDRESS DECODE
R MUX DAC B
DUTGND B VOUTC
R X1 DATA REG D MUX DAC D VOUTD R DATA REG E X1 X1 R DUTGND D X1 R DUTGND C
DGND
AGND
SEL
VREF(+)D VREF(-)D
VREF(+)C VREF(-)C
CLR
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD7836-SPECIFICATIONS
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Full-Scale Error Zero-Scale Error Gain Error Gain Temperature Coefficient2 DC Crosstalk2 REFERENCE INPUTS DC Input Resistance Input Current VREF(+) Range VREF(-) Range [VREF(+) - VREF(-)] OUTPUT CHARACTERISTICS Output Voltage Swing Short Circuit Current Resistive Load Capacitive Load DIGITAL INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance POWER REQUIREMENTS VCC VDD VSS Power Supply Sensitivity Full Scale/VDD Full Scale/VSS ICC IDD ISS A 14 2 0.9 8 8 2 20 40 50 100 1 0/+5 -5/0 2/10
(VCC = +5 V 5%; VDD = +15 V 5%; VSS = -15 V 5%; AGND = DGND = DUTGND = 0 V; RL = 5 k and CL = 50 pF to GND, TA1 = TMIN to TMAX, unless otherwise noted)
Test Conditions/Comments
Units Bits LSB max LSB max LSB max LSB max mV typ ppm FSR/C typ ppm FSR/C max V max M typ A max V min/max V min/max V min/max
Guaranteed Monotonic Over Temperature VREF(+) = +5 V, VREF(-) = -5 V. Typically within 1 LSB VREF(+) = +5 V, VREF(-) = -5 V. Typically within 1 LSB VREF(+) = +5 V, VREF(-) = -5 V See Terminology. R L = 5 k
Per Input. Typically 20 nA For Specified Performance. Can Go as Low as 0 V, but Performance Not Guaranteed 2 x (VREF(-)+[VREF(+)-VREF(-)]*D) - VDUTDGN To 0 V To 0 V
10 25 5 50 2.4 0.8 10 10 5.0 15.0 -15.0 110 100 0.5 8 14 14
V min mA max k min pF max V min V max A max pF max V nom V nom V nom dB typ dB typ mA max mA max mA max mA max
Total for All Pins
5% for Specified Performance 5% for Specified Performance 5% for Specified Performance
VINH = VCC, VINL = DGND. Dynamic Current VINH = 2.4 V min, VINL = 0.8 V max Outputs Unloaded. Typically 7 mA Outputs Unloaded. Typically 7 mA
AC PERFORMANCE CHARACTERISTICS subject to production testing.)
Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time Digital-to-Analog Glitch Impulse DC Output Impedance Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk Digital Feedthrough Output Noise Spectral Density @ 1 kHz
NOTES 1 Temperature range for A Version: -40C to +85C 2 Guaranteed by design. Specifications subject to change without notice.
(These characteristics are included for Design Guidance and are not
Test Conditions/Comments Full-Scale Change to 1/2 LSB. DAC Latch Contents Alternately Loaded with All 0s and All 1s Measured with VREF(+) = +5 V, VREF(-) = -5 V. DAC Latch Alternately Loaded with 1FFF Hex and 2000 Hex. Not Dependent on Load Conditions See Terminology See Terminology See Terminology Feedthrough to DAC Output Under Test Due to Change in Digital Input Code to Another Converter Effect of Input Bus Activity on DAC Output Under Test All 1s Loaded to DAC. V REF(+) = VREF(-) = 0 V
A 16 150 0.3 115 10 10 0.2 40
Units s typ nV-s typ max dB typ nV-s typ nV-s typ nV-s typ nV/Hz typ
-2-
REV. A
AD7836 TIMING SPECIFICATIONS1
Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 15 0 0 0 44 15 4.5 44 16 300
(VCC = +5 V
5%; VDD = +15 V
5%; VSS = -15 V
5%; AGND = DGND = 0 V)
Description A0, A1, A2 to WR Setup Time A0, A1, A2 to WR Hold Time CS to WR Setup Time WR to CS Hold Time WR Pulsewidth Data Setup Time Data Hold Time WR Pulse Interval Settling Time CLR Pulse Activation Time
Limit at TMIN, TMAX
Units ns min ns min ns min ns min ns min ns min ns min ns min s typ ns max
NOTES 1 All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 Rise and fall times should be no longer than 50 ns. Specifications subject to change without notice.
t1
A0, A1, A2
t2
t3
CS
t4
t8
WR
t5 t6 t7
DATA
t9
VOUT
t 10
CLR
VOUT
Figure 1. Timing Diagram
REV. A
-3-
AD7836
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise noted)
VCC to DGND . . . . . . . . . . . . . . .-0.3 V, +7 V or VDD + 0.3 V (Whichever Is Lower) VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +17 V VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, -17 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +0.3 V Digital Inputs to DGND . . . . . . . . . . . . . -0.3 V, VCC + 0.3 V VREF(+) to VREF(-) . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +18 V VREF(+) to AGND . . . . . . . . . . . . . . VSS - 0.3 V, VDD + 0.3 V VREF(-) to AGND . . . . . . . . . . . . . . VSS - 0.3 V, VDD + 0.3 V DUTGND to AGND . . . . . . . . . . . VSS - 0.3 V, VDD + 0.3 V VOUT (A-D) to AGND . . . . . . . . . . VSS - 0.3 V, VDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150C
MQFP Package, Power Dissipation . . . . . . . . . . . . . . 480 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Model AD7836AS
Temperature Range -40C to +85C
Linearity Error (LSBs) 2
DNL (LSBs) 0.9
Package Option* S-44
*S = Plastic Quad Flatpack (MQFP).
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7836 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. A
AD7836
PIN DESCRIPTION
Pin Mnemonic VCC VSS VDD DGND AGND VREF(+)A, VREF(-)A VREF(+)B, VREF(-)B VREF(+)C, VREF(-)C VREF(+)D, VREF(-)D VOUTA . . . VOUTD CS DB0 . . . DB13 A0, A1, A2 CLR
Description Logic Power Supply; +5 V 5%. Negative Analog Power Supply; -15 V 5%. Positive Analog Power Supply; +15 V 5%. Digital Ground. Analog Ground. Reference Inputs for DAC A. These reference voltages are referred to AGND. Reference Inputs for DAC B. These reference voltages are referred to AGND. Reference Inputs for DAC C. These reference voltages are referred to AGND. Reference Inputs for DAC D. These reference voltages are referred to AGND. DAC Outputs. Level-Triggered Chip Select Input (active low). The device is selected when this input is low. Parallel Data Inputs. The AD7836 can accept a straight 14-bit parallel word on DB0 to DB13 where DB13 is the MSB and DB0 is the LSB. Address inputs. A0, A1 and A2 are decoded to select one of the five input latches for a data transfer. Asynchronous Clear Input (level sensitive, active low). When this input is low, all analog outputs are switched to the externally set potential on the DUTGND pin. The contents of data registers A to E are not affected when the CLR pin is taken low. When CLR is brought back high, the DAC outputs revert back to their original outputs as determined by the data in their data registers. Level-Triggered Write Input (active low), when active and used in conjunction with CS to write data to the AD7836 input buffer. Data is latched into the selected data register on the rising edge of WR. Device Sense Ground for DAC A. Vout A is referenced to the voltage applied to this pin. Device Sense Ground for DAC B. Vout B is referenced to the voltage applied to this pin. Device Sense Ground for DAC C. Vout C is referenced to the voltage applied to this pin. Device Sense Ground for DAC D. Vout D is referenced to the voltage applied to this pin. Select pin, active high level triggered input. When the SEL input is high, the user programmed value in DATAREG E will be loaded into all DAC registers and the DAC outputs updated accordingly. The contents of the other DATA REGs (A-D) will not be affected by the SEL pin.
PIN CONFIGURATION
DUTGND C DUTGND D
WR DUTGND A DUTGND B DUTGND C DUTGND D SEL
VREF(+)D
VREF(-)D
VOUTD
DB13
DB12
DB11
DB10
DB9
33 32 31 30 29 28 27 26 25 24 23 VOUTC 34 VREF(-)C 35 VREF(+)C 36 AGND 37 NC 38 VDD 39 NC 40 VSS 41 VREF(+)A 42 VREF(-)A 43 VOUTA 44 1
DUTGND A
PIN 1 IDENTIFIER
DB8
22 DB7 21 DB6 20 DB5 19 DB4
AD7836
TOP VIEW (Not to Scale)
18 DB3 17 DB2 16 DB1 15 DB0 14 DGND 13 VCC 12 CLR
2
VREF(+)B
3
VREF(-)B
4
VOUTB
5
DUTGND B
6
A2
7
A1
8
A0
9 10 11
SEL CS WR
NC = NO CONNECT
REV. A
-5-
AD7836
TERMINOLOGY Relative Accuracy Full-Scale Error
Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error and is normally expressed in Least Significant Bits or as a percentage of full-scale reading.
Differential Nonlinearity
This is the error in DAC output voltage when all 1s are loaded into the DAC latch. Ideally the output voltage, with all 1s loaded into the DAC latch, should be 2 VREF(+) - 1 LSB. Fullscale error does not include zero-scale error.
Zero-Scale Error
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity.
DC Crosstalk
Zero-scale error is the error in the DAC output voltage when all 0s are loaded into the DAC latch. Ideally the output voltage, with all 0s in the DAC latch should be equal to 2 VREF(-). Zeroscale error is mainly due to offsets in the output amplifier.
Gain Error
Gain Error is defined as (Full-Scale Error) - (Zero-Scale Error).
GENERAL DESCRIPTION DAC Architecture--General
Although the common input reference voltage signals are internally buffered, small IR drops in the individual DAC reference inputs across the die can mean that an update to one channel can produce a dc output change in one or other of the channel outputs. The four DAC outputs are buffered by op amps that share common VDD and VSS power supplies. If the dc load current changes in one channel (due to an update), this can result in a further dc change in one or other channel outputs. This effect is most obvious at high load currents and reduces as the load currents are reduced. With high impedance loads the effect is virtually unmeasurable.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse
This is the amount of charge injected into the analog output when the inputs change state. It is specified as the area of the glitch in nV-secs. It is measured with VREF(+) = +5 V and VREF(-) = -5 V and the digital inputs toggled between 1FFFHEX and 8000H.
Channel-to-Channel Isolation
Each channel consists of a segmented 14-bit R-2R voltage-mode DAC. The full-scale output voltage range is equal to twice the reference span of VREF(+) - VREF(-). The DAC coding is straight binary; all 0s produces an output of 2 VREF(-); all 1s produces an output of 2 VREF(+) - 1 LSB. The analog output voltage of each DAC channel reflects the contents of its own DAC latch. Data is transferred from the external bus to the input register of each DAC latch on a per channel basis. The AD7836 has a feature whereby using the A2 pin, data can be transferred from the input data bus to all four input registers simultaneously. Bringing the CLR line low switches all the signal outputs, VOUTA to VOUTD, to the voltage level on the DUTGND pin. When CLR signal is brought back high the output voltages from the DACs will reflect the data stored in the relevant DAC registers.
Data Loading to the AD7836
Data is loaded into the AD7836 in straight parallel 14-bit wide words. The DAC output voltages, VOUTA-VOUTD are updated to reflect new data in the DAC input registers. The actual DAC input register that is being written to is determined by the logic levels present on the devices address lines, as shown in Table I.
Table I. Address Line Truth Table
Channel-to-channel isolation refers to the proportion of input signal from one DACs reference input that appears at the output of the other DAC. It is expressed in dBs.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is defined as the glitch impulse that appears at the output of one converter due to both the digital change and subsequent analog O/P change at another converter. It is specified in nV-s.
Digital Crosstalk
A2 0 0 0 0 1 1
A1 0 0 1 1 0 1
A0 0 1 0 1 0 1
DAC Selected DATA REG A (DAC A) DATA REG B (DAC B) DATA REG C (DAC C) DATA REG D (DAC D) DATA REG E DATA REG A-D
The glitch impulse transferred to the output of one converter due to a change in digital input code to the other converter is defined as the digital crosstalk and is specified in nV-s.
Digital Feedthrough
When the device is not selected, high frequency logic activity on the device's digital inputs can be capacitively coupled both across and through the device to show up as noise on the VOUT pins. This noise is digital feedthrough.
DC Output Impedance
This is the effective output source resistance. It is dominated by package lead resistance.
-6-
REV. A
Typical Performance Characteristics-AD7836
1.0 0.8
0.6 0.9
2 VDD = 15V VSS = -15V VREF(+) = +5V VREF(-) = -5V
0.6
INL ERROR - LSBs
0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2 4 6 8 10 12 INPUT CODE/1000 14 16
0.2 0.0 -0.2 -0.4 -0.6 -0.9 0 2 4 6 8 10 12 INPUT CODE/1000 14 16
INL ERROR - LSB
0.4
DNL ERROR - LSBs
0.4
1
0
-1
-2 -40
-20
0 20 40 60 TEMPERATURE - C
80 90
Figure 2. Typical INL Plot
Figure 3. Typical DNL Plot
Figure 4. Typical INL Error vs. Temperature
1.0 VDD = 15V VSS = -15V VREF(+) = +5V VREF(-) = -5V
ERROR - LSB
2 VDD = 15V VSS = -15V VREF(+) = +5V VREF(-) = -5V
ICC - mA
6 DIGITAL INPUTS @ THRESHOLDS 5 4 VCC = 5V VDD = 15V VSS = -15V
0.5
DNL ERROR - LSB
1
FULL-SCALE ERROR 0
3 2 1
0
OFFSET ERROR -0.5 -1
DIGITAL INPUTS @ SUPPLIES 0
-1.0 -40
-20
0 20 40 60 TEMPERATURE - C
80 90
-2 -40
-20
0 20 40 60 TEMPERATURE - C
80 90
-1 -40
-20
0 20 40 60 TEMPERATURE - C
80 90
Figure 5. Typical DNL Error vs. Temperature
Figure 6. Offset and Full-Scale Error vs. Temperature
Figure 7. ICC vs. Temperature
0.7 0.6 0.5 0.4 0.3 0.2 0.1 VERT = 100mV/DIV HORIZ = 1 s/DIV
10.2
8
10.0 IDD/ISS - mA
7 VDD = 15V VSS = -15V VREF(+) = +5V VREF(-) = -5V
VOUT - V
9.8
6
9.6
5
0 -0.1 -0.2
9.4
4 -40
9.2 11
12 13 SETTLING TIME - s
14
-20
0 20 40 60 TEMPERATURE - C
80 90
Figure 8. Typical Digital/Analog Glitch Impulse
Figure 9. Settling Time (+)
Figure 10. IDD/ISS vs. Temperature
REV. A
-7-
AD7836
Unipolar Configuration
Figure 11 shows the AD7836 in the unipolar binary circuit configuration. The VREF(+) input of the DAC is driven by the AD586, a +5 V reference. VREF(-) is tied to ground. Table II gives the code table for unipolar operation of the AD7836. Other suitable references include the REF02, a precision 5 V reference, and the REF195, a low dropout, micropower precision +5 V reference.
+15V +5V
When bipolar-zero and full-scale adjustment are not needed, R2 and R3 can be omitted. Pin 12 on the AD588 should be connected to Pin 11 and Pin 5 should be left floating.
+15V R1 39k 4 7 C1 1F R2 100k 9 6 2 3 1 14 15 16 12 8 13 -15V *ADDITIONAL PINS OMITTED FOR CLARITY VREF(-) VDD VREF(+) VCC VOUT VOUT (-10V TO +10V) +5V
AD588
2 6 8 C1 1nF AD586 4 VREF(-) VSS SIGNAL GND -15V *ADDITIONAL PINS OMITTED FOR CLARITY SIGNAL GND 5 R1 10k VDD VREF(+) VCC VOUT DUTGND AGND DGND VOUT (0 TO +10V)
AD7836*
DUTGND AGND VSS DGND SIGNAL GND
5 10 11 R3 100k
AD7836*
Figure 12. Bipolar 5 V Operation
Table III. Code Table for Bipolar Operation
Binary Number in DAC Latch MSB LSB 11 10 10 01 00 00 1111 0000 0000 1111 0000 0000 1111 0000 0000 1111 0000 0000 1111 0001 0000 1111 0001 0000 Analog Output (VOUT) 2[VREF(-) + VREF (16383/16384)] V 2[VREF(-) + VREF (8193/16384)] V 2[VREF(-) + VREF (8192/16384)] V 2[VREF(-) + VREF (8191/16384)] V 2[VREF(-) + VREF (1/16384)] V 2[VREF(-)] V
Figure 11. Unipolar +5 V Operation
Offset and gain may be adjusted in Figure 2 as follows: To adjust offset, disconnect the VREF(-) input from 0 V, load the DAC with all 0s and adjust the VREF(-) voltage until VOUT = 0 V. For gain adjustment, the AD7836 should be loaded with all 1s and R1 adjusted until VOUT = 10 V(16383/16384) = 9.999389. Many circuits will not require these offset and gain adjustments. In these circuits R1 can be omitted. Pin 5 of the AD586 may be left open circuit and Pin 2 (VREF(-)) of the AD7836 tied to 0 V.
Table II. Code Table for Unipolar Operation
Binary Number in DAC Latch MSB LSB 11 10 01 00 00 1111 0000 1111 0000 0000 1111 0000 1111 0000 0000 1111 0000 1111 0001 0000
Analog Output (VOUT) 2 VREF (16383/16384) V 2 VREF (8192/16384) V 2 VREF (8191/16384) V 2 VREF (1/16384) V 0V
NOTE VREF = (VREF(+) - VREF(-)). For VREF(+) = +5 V, and V REF(-) = -5 V, V REF =10 V, 1 LSB = 2 VREF V/2 14 = 20 V/16384 = 1220 V.
CONTROLLED POWER-ON OF THE OUTPUT STAGE
NOTE VREF = VREF(+); VREF(-) = 0 V for unipolar operation. For VREF(+) = +5 V, 1 LSB = +10 V/2 14 = +10 V/16384 = 610 V.
A block diagram of the output stage of the AD7836 is shown in Figure 13. It is capable of driving a load of 5 k in parallel with 50 pF. G1 to G6 are transmission gates that are used to control the power on voltage present at VOUT. On power up G1 and G2 are also used in conjunction with the CLR input to set VOUT to the user defined voltage present at the DUTGND pin. When CLR is taken back high the DAC outputs reflect the data in the DAC registers.
G1 DAC G3 G2 G4 G6 VOUT
Bipolar Configuration
Figure 12 shows the AD7836 set up for 10 V operation. The AD588 provides precision 5 V tracking outputs that are fed to the VREF(+) and VREF(-) inputs of the AD7836. The code table for bipolar operation of the AD7836 is shown in Table III. In Figure 12, full-scale and bipolar zero adjustments are provided by varying the gain and balance on the AD588. R2 varies the gain on the AD588 while R3 adjusts the offset of both the +5 V and -5 V outputs together with respect to ground. For bipolar-zero adjustment, the DAC is loaded with 1000 . . . 0000 and R3 is adjusted until VOUT = 0 V. Full scale is adjusted by loading the DAC with all 1s and adjusting R2 until VOUT = 10(8191/8192) V = 9.998779 V.
R = 13.5k G5
R
6k
DUTGND
Figure 13. Block Diagram of AD7836 Output Stage
-8-
REV. A
AD7836
Power-On with CLR Low
G1 DAC G3 G2 G4 G6 VOUT
The output stage of the AD7836 has been designed to allow output stability during power-on. If CLR is kept low during power-on, then just after power is applied to the AD7836, the situation is as depicted in Figure 14. G1, G4 and G6 are open while G2, G3 and G5 are closed.
G1 DAC G3 G2 G4 G6 VOUT
R G5
R
6k
DUTGND
Figure 16. Output Stage After CLR Is Taken High
R G5
Power-On with CLR High
6k
R
DUTGND
Figure 14. Output Stage with VDD < 10 V
VOUT is kept within a few hundred millivolts of DUTGND via G5 and a 6k resistor. This thin-film resistor is connected in parallel with the gain resistors of the output amplifier. The output amplifier is connected as a unity gain buffer via G3, and the DUTGND voltage is applied to the buffer input via G2. The amplifier's output is thus at the same voltage as the DUTGND pin. The output stage remains configured as in Figure 14 until the voltage at VDD and VSS reaches approximately 10 V. By now the output amplifier has enough headroom to handle signals at its input and has also had time to settle. The internal power-on circuitry opens G3 and G5 and closes G4 and G6. This situation is shown in Figure 15. Now the output amplifier is configured in its noise gain configuration via G4 and G6. The DUTGND voltage is still connected to the noninverting input via G2 and this voltage appears at VOUT.
G1 DAC G3 G2 G4 G6 VOUT
If CLR is high on the application of power to the device, the output stages of the AD7836 are configured as in Figure 17 while VDD/VSS are less than 10 V. G1 is closed and G2 is open thereby connecting the output of the DAC to the input of its output amplifier. G3 and G5 are closed while G4 and G6 are open thus connecting the output amplifier as a unity gain buffer. VOUT is connected to DUTGND via G5 through a 6 k resistor until VDD and VSS reach approximately 10 V.
G1 DAC G3 G2 G4 G6 VOUT
R G5
R
6k
DUTGND
Figure 17. Output Stage Powering Up with CLR High While VDD/VSS < 10 V
When the supplies reach 10 V, the internal power on circuitry opens G3 and G5 and closes G4 and G6 configuring the output stage as shown in Figure 18.
G1 G6 VOUT
R G5
DAC G3 G2 G4
R
6k
DUTGND
R G5
Figure 15. Output Stage with VDD > 10 V and CLR Low
R
6k
VOUT has been disconnected from the DUTGND pin by the opening of G5 but will track the voltage present at DUTGND via the configuration shown in Figure 15. When CLR is taken back high, the output stage is configured as shown in Figure 16. The internal control logic closes G1 and opens G2. The output amplifier is connected in a noninverting gain of two configuration. The voltage that appears on the Vout pins is determined by the data present in the DAC registers. To set all output voltages to the same known state, a write to DATA REG E with the SEL pin high allows all DAC registers to be updated with the same data.
DUTGND
Figure 18. Output Stage Powering Up with CLR High When VDD/VSS > 10 V
REV. A
-9-
AD7836
DUTGND Voltage Range
During power-on, the VOUT pins of the AD7836 are connected to the relevant DUTGND pins via G6 and the 6 k thin-film resistor. The DUTGND potential must obey the max ratings at all times. Thus, the voltage at DUTGND must always be within the range VSS - 0.3 V, VDD + 0.3 V. However, in order that the voltages at the VOUT pins of the AD7836 stay within 2 V of the relevant DUTGND potential during power-on, the voltage applied to DUTGND should also be kept within the range AGND - 2 V, AGND + 2 V. Once the AD7836 has powered on and the on-chip amplifiers have settled, any voltage that is now applied to the DUTGND pin is subtracted from the DAC output which has been gained up by a factor of two. Thus, for specified operation, the maximum voltage that can be applied to the DUTGND pin increases to the maximum allowable 2 x VREF(+) voltage, and the minimum voltage that can be applied to DUTGND is the minimum 2 x VREF(-) voltage. After the AD7836 has fully powered on, the outputs can track any DUTGND voltage within this minimum/maximum range.
MICROPROCESSOR INTERFACING Interfacing the AD7836--16-Bit Interface
APPLICATIONS Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD7836 is mounted should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should only be joined at one place. If the AD7836 is the only device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD7836. If the AD7836 is in a system where multiple devices require an AGND to DGND connection, the connection should still be made at one point only, a star ground point which should be established as close as possible to the AD7836. Digital lines running under the device should be avoided as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7836 to avoid noise coupling. The power supply lines of the AD7836 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but not always possible with a double sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. The AD7836 should have ample supply bypassing located as close to the package as possible, ideally right up against the device. Figure 20 shows the recommended capacitor values of 10 F in parallel with 0.1 F on each of the supplies. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitor should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.
The AD7836 can be interfaced to a variety of 16-bit microcontrollers or DSP processors. Figure 19 shows the AD7836 interfaced to a generic 16-bit microcontroller/DSP processor. The lower address lines from the processor are connected to A0, A1 and A2 on the AD7836 as shown. The upper address lines are decoded to provide a chip select signal for the AD7836. They are also decoded (in conjunction with the lower address lines if need be) to provide a SEL signal. The fast interface timing of the AD7836 allows direct interface to a wide variety of microcontrollers and DSPs as shown in Figure 19.
CONTROLLER/ DSP PROCESSOR* D13 DATA BUS
AD7836*
* * *
D13
* * *
D0 UPPER BITS OF ADDRESS BUS ADDRESS DECODE
D0 CS
A2 A1 A0 R/W
A2 A1 A0 WR
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 19. AD7836 Parallel Interface
0.1 F 10 F
VCC
VDD 10 F 0.1 F
AD7836
VSS 10 F 0.1 F
Figure 20. Recommended Decoupling Scheme for AD7836
-10-
REV. A
AD7836
Automated Test Equipment
The AD7836 is particularly suited for use in an automated test environment. Figure 21 shows the AD7836 providing the necessary voltages for the pin driver and the window comparator in a typical ATE pin electronics configuration. AD588s are used to provide reference voltages for the AD7836. In the configuration shown, the AD588s are configured so that the voltage at Pin 1 is 5 V greater than the voltage at Pin 9 and the voltage at Pin 15 is 5 V less than the voltage at Pin 9.
+15V -15V 2 4 6 8 13 7 1F 10 11 12 +15V -15V 2 4 6 8 13 10 11 12 1F 7 8 DEVICE GND 16 3 1 AD588 15 14 VOUTC VREF(+)C/D VREF(-)C/D AGND WINDOW COMPARATOR TO TESTER VOUTD DEVICE GND 16 3 1 AD588 15 14 9 0.1 F VREF(+)A/B VREF(-)A/B DUTGND A/B VOUTB -15V VOUTA +15V VOFFSET
Programmable Reference Generation for the AD7836 in an ATE Application
PIN DRIVER
The AD7836 is particularly suited for use in an automated test environment. The reference input for the AD7836 quad 14-bit DAC requires two references for each DAC. Programmable references may be a requirement in some ATE applications as the offset and gain errors at the output of each DAC can be adjusted by varying the voltages on the reference pins of the DAC. To trim offset errors, the DAC is loaded with the digital code 000 . . . 000 and the voltage on the VREF(-) pin is adjusted until the desired negative output voltage is obtained. To trim out gain errors, first the offset error is trimmed. Then the DAC is loaded with the code 111 . . . 111 and the voltage on the VREF(+) pin is adjusted until the desired full scale voltage minus one LSB is obtained. It is not uncommon in ATE design, to have other circuitry at the output of the AD7836 that can have offset and gain errors of up to say 300 mV. These offset and gain errors can be easily removed by adjusting the reference voltages of the AD7836. The AD7836 uses nominal reference values of 5 V to achieve an output span of 10 V. Since the AD7836 has a gain of two from the reference inputs to the DAC output, adjusting the reference voltages by 150 mV will adjust the DAC offset and gain by 300 mV. There are a number of suitable 8- and 10-bit DACs available that would be suitable to drive the reference inputs of the AD7836, such as the AD7804 which is a quad 10-bit digital-toanalog converter with serial load capabilities. The voltage output from this DAC is in the form of VBIAS VSWING and rail to rail operation is achievable. The voltage reference for this DAC can be internally generated or provided externally. This DAC also contains an 8-bit SUB DAC which can be used to shift the complete transfer function of each DAC around the VBIAS point. This can be used as a fine trim on the output voltage. In this Application two AD7804s are required to provide programmable reference capability for all four DACs. One AD7804 is used to drive the VREF(+) pins and the second package used to drive the VREF(-) pins. Another suitable DAC for providing programmable reference capability is the AD8803. This is an octal 8-bit trimDAC(R) and provides independent control of both the top and bottom ends of the trimDAC. This is helpful in maximizing the resolution of devices with a limited allowable voltage control range. The AD8803 has an output voltage range of GND to VDD (0 V to +5 V). To trim the VREF(+) input, the appropriate trim range on the AD8803 DAC can be set using the VREFL and VREFH pins allowing 8 bits of resolution between the two points. This will allow the VREF(+) pin to be adjusted to remove gain errors. To trim the VREF(-) voltage, some method of providing a trim voltage in the required negative voltage range is required. Neither the AD7804 or the AD8803 can provide this range in normal operation as their output range is 0 V to +5 V. There are two methods of producing this negative voltage. One method is to provide a positive output voltage and then to level shift that analog voltage to the required negative range. Alternatively
AD7836*
DUTGND C/D
DEVICE GND
VOUT
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. ATE Application
One of the AD588s is used as a reference for DACs 1 and 2. These DACs are used to provide high and low levels for the pin driver. The pin driver may have an associated offset. This can be nulled by applying an offset voltage to Pin 9 of the AD588. First, the code 1000 . . . 0000 is loaded into the DACA latch and the pin driver output is set to the DACA output. The VOFFSET voltage is adjusted until 0 V appears between the pin driver output and DUT GND. This causes both VREF(+) and VREF(-) to be offset with respect to AGND by an amount equal to VOFFSET. However, the output of the pin driver will vary from -10 V to +10 V with respect to DUT GND as the DAC input code varies from 000 . . . 000 to 111 . . . 111. The VOFFSET voltage is also applied to the DUTGND pins. When a clear is performed on the AD7836, the output of the pin driver will be 0 V with respect to Device GND. The other AD588 is used to provide a reference voltage for DACs C and D. These provide the reference voltages for the window comparator shown in the diagram. Note that Pin 9 of this AD588 is connected to Device GND. This causes VREF(+)C & D and VREF(-)C & D to be referenced to Device GND. As DAC 3 and DAC 4 input codes vary from 000 . . . 000 to 111 . . . 111, VOUT3 and VOUT4 vary from -10 V to +10 V with respect to Device GND. Device GND is also connected to DUTGND. When the AD7836 is cleared, VOUTC and VOUTD are cleared to 0 V with respect to DEVICE GND.
TrimDAC is a registered trademark of Analog Devices, Inc.
REV. A
-11-
AD7836
these DACs can be operated with supplies of 0 V and a -5 V, with the VDD pin connected to 0 V and the GND pin connected to -5 V. Now these can be used to provide the negative reference voltages for the VREF(-) inputs on the AD7836. However, the digital signals driving the DACs need to be level shifted from the 0 V to +5 V range to the -5 V to 0 V range. Figure 22 shows a typical application circuit to provide programmable reference capabilities for the AD7836.
ADDR BUS +5V ADDR DECODER FSIN/CS SDATA SCLK DIN SCLK GND LOGIC LEVEL SHIFT 8/10-BIT DAC VDD 0V to -5V
8/10-BIT DAC
VDD A0,A1,A2 0V to 5V VREF(+)A VOUTA VOUT
AD7836*
CONTROLLER
FSIN/CS DIN SCLK
VREF(-) A
GND
-5V DATA BUS DATA BUS AGND
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. Programmable Reference Generation for the AD7836
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead MQFP (S-44)
0.096 (2.44) MAX 0.037 (0.94) 0.025 (0.64) SEATING PLANE 8 0.8
34 33
0.548 (13.925) 0.546 (13.875) 0.398 (10.11) 0.390 (9.91)
23 22
TOP VIEW
(PINS DOWN)
44
12 1 11
0.040 (1.02) 0.032 (0.81) 0.083 (2.11) 0.077 (1.96)
0.040 (1.02) 0.032 (0.81)
0.033 (0.84) 0.029 (0.74)
0.016 (0.41) 0.012 (0.30)
-12-
REV. A
PRINTED IN U.S.A.
C2163a-0-9/99

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